1. Field of the Invention
The present invention relates to circuit board structures and a method for fabricating the same, and more particularly, to a circuit board structure with a semiconductor chip embedded therein and a method for fabricating the same.
2. Description of the Prior Art
As the semiconductor package technology continues to evolve, many different types of semiconductor devices have been developed. Fabrication of a semiconductor package comprises the steps of mounting a semiconductor chip on a package substrate or a lead frame, electrically connecting the semiconductor chip to the package substrate or the lead frame, and performing an encapsulation process using an encapsulant. Among these different types of semiconductor devices, a ball grid array (BGA) package represents advanced semiconductor package technology, which features utilizing a package substrate with a plurality of solder balls aligned in grid array and formed on the back surface of the package substrate for electrically connecting a semiconductor chip to external devices, such that more I/O connections can be accommodated within the same unit area of a surface of the semiconductor chip carrier so as to cater for the high-integration semiconductor chip.
In the traditional semiconductor package, the semiconductor chip is attached to the top surface of the substrate and undergoes wire bonding packaging or connected with a flip chip packaging, then the back surface of the substrate is implanted with a plurality of solder balls for electrical connection with the semiconductor chip, thus achieving a high pin number. But the undesirably long connection path of the bonding wires may bring about increased impedance, thereby making it difficult to enhance the electrical performance during high-frequency use or high-speed operation. Moreover, traditional packages require connecting an interface repeatedly which undesirably increase the fabricating cost.
In order to effectively enhance the electrical performance to meet the requirement for applications of the next generation electronic devices, the semiconductor package industry is devoted to the research in embedding a semiconductor chip in the carrier board for establishing direct electrical connection in order to reduce the length of the electrical transmission pathway as well as reduce signal loss and signal distortion, thereby improving high-speed operation.
FIG. 1 shows a cross-sectional schematic view of a conventional semiconductor package in which a semiconductor element is embedded in a substrate. A method for fabricating the conventional semiconductor package with an embedded semiconductor element comprises: preparing a carrier board 10 having a first surface 101 and an opposing second surface 102; forming at least one through hole 100 penetrating the carrier board 10 from the first surface 101 to the second surface 102 of the carrier board 10; receiving a semiconductor chip 11 in the through hole 100 and securing the semiconductor chip 11 to the through hole 100 by a glue material 110, wherein the semiconductor chip 11 has an active surface 11a and a non-active surface 11b opposing the active surface 11a, the active surface 11a having a plurality of electrode pads 111 formed thereon; forming a circuit build up structure 12 on the first surface 101 of the carrier board 10 and the active surface 11a of the semiconductor chip 11, wherein the circuit build up structure 12 further comprises a dielectric layer 120, a circuit layer 121 stacked on the dielectric layer 120, and conductive vias 122 formed in the dielectric layer 120 and electrically connected to the electrode pads 111 of the semiconductor chip 11.
Although the foregoing chip-embedded semiconductor package can solve various drawbacks of the prior art, the foregoing circuit build up structure 12 is formed on a single surface, that is, the first surface 101 of the carrier board 10, thus resulting in asymmetry of the circuit board in terms of structure. The structural asymmetry is accompanied by unbalanced thermal stress during a fabrication process that features an increasing number of circuit layers, and variation of temperature during, for example, substrate baking, and a thermal cycle. The unbalanced thermal stress tends to cause problems, such as warpage of the substrate structure, interlayer delamination, and even chip cracking.
Thus, there is an urgent need for developing a chip-embedded semiconductor package to overcome drawbacks of the prior art, such as warpage and high production cost.